The present invention relates generally to a metal-insulator-metal (MIM) capacitor, and more particularly, to a configuration in which capacitor plate portions are formed on sidewall surfaces of a via, trench, or other cavity to provide a three-plate vertical MIM capacitor structure with only one patterning/mask fabrication process.
Capacitors are widely used in the semiconductor devices. Such capacitive structures include, for example, metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors and metal-insulator-metal (MIM) capacitors. MIM capacitors can provide certain advantages over MOS and p-n junction capacitors because the frequency characteristics of MOS and p-n junction capacitors may be restricted as a result of depletion layers that form in the semiconductor electrodes. A MIM capacitor can therefore exhibit improved frequency and temperature characteristics.
MIM capacitors are typically formed in successive metal interconnect layers of the back end of the line (BEOL) stage of the chip fabrication, the fabrication stage in which multiple metal interconnect layers interconnect the components and nodes, including components formed in the substrate during the front end of the line (FEOL) processing. Conventional MIM capacitors utilize a so-called “2-plate” structure in which the MIM capacitor includes two metal plates. Recently, techniques have considered a “3-plate” structure, which includes three metal plates, and that shows about twice the performance of 2-plate structures, as exemplarily shown in FIG. 1. As can be seen in FIG. 1 and for purpose of the present invention, the term “3-plate” refers to a MIM capacitor structure which, in cross section, includes two plate portions of one polarity of the capacitor electrically interconnected so as to surround or envelope on opposing sides a third plate portion of the opposite polarity of the capacitor, along with the dielectric material used to separate two capacitor plates of opposite polarities.
However, to one of ordinary skill, this “3-plate” structure 100 shown in FIG. 1 has a relatively complex fabrication that requires three additional masks, each including a lithography and reactive ion etching (RIE) process, which results in a relatively high manufacturing cost. In addition, there is a limited horizontal area on a chip, which can lead to performance or scaling challenges for this conventional 3-plate structure.